Semiconductor device designers often desire to increase the level of integration, which may also be characterized in terms of density, of features within a semiconductor device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, semiconductor device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.
One example of a semiconductor device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many types of memory including, but not limited to, random-access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), Flash memory, and resistance variable memory. Non-limiting examples of resistance variable memory include resistive random access memory (RRAM), conductive bridge random access memory (conductive bridge RAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin-torque-transfer random access memory (STT-RAM), oxygen vacancy-based memory, and programmable conductor memory.
Various semiconductor device structures (e.g., various memory device structures) are formed using a plurality of processing acts, which often include forming different features (e.g., contact structures, routing structures) aligned with one another over a substrate. Failure to achieve sufficient alignment of the features can render a semiconductor device including the misaligned features inoperative. A conventional way of providing requisite feature alignment is through the use of alignment marks (also referred to in the art as “registration marks”). For example, a mask including an integrated circuit pattern and an alignment mark pattern therein may be utilized in a photolithography process to transfer the integrated circuit pattern and the alignment mark pattern to a photoresist material overlying a substrate, wherein the substrate exhibits an additional alignment mark pattern thereon or therein. The photoresist material is then developed to form a patterned photoresist material exhibiting the integrated circuit pattern and the alignment mark pattern of the mask. Thereafter, the alignment mark pattern of the patterned photoresist material is inspected for alignment with the additional alignment mark pattern of the underlying substrate. If the alignment mark pattern of the patterned photoresist material is not sufficiently aligned with the additional alignment mark pattern of the underlying substrate, the patterned photoresist material is removed (e.g., stripped), re-applied, re-photoexposed, re-developed, and re-inspected for alignment mark pattern misalignment. Such additional, misalignment-imposed processing is inefficient and costly (e.g., increasing processing time as well as energy and material costs).
It would, therefore, be desirable to have new methods of forming semiconductor device structures having aligned features that mitigate one or more of the problems associated with conventional methods of forming such semiconductor device structures.